EMC Test Master for IO-Link

The IO-Link specification defines procedures for testing the EMC robustness of IO-Link devices. Among other things, the sensitivity of IO-Link communication of IO-Link devices under EMC conditions is verified. This requires a robust master that is significantly less sensitive to EMC noise than the device under test. This is achieved by separating the IO-Link Master into two parts: Part 1 contains the sensitive digital logic (µC box), and Part 2 contains the IO-Link transceiver (PHY box).
Both parts are separated by an optical connection with a length of up to 10 m.

EMV Test Master IO-Link

EMC Test System Specifications

  • Complies with IO-Link Interface Specification V1.1.2 and the current IO-Link Test Specification.
  • Error and signal output
  • 4 electrical IO-Link port configurations
    COM1 / 2 port (good signal)
    COM1 / 2 port (bad signal)
    COM3 port (good signal)
    COM3 port (bad signal)
  • RS232 and USB interfaces
  • Terminal-based control command set
  • Additional EMC test and control software with graphical user interface
  • Test report generation in PDF format
  • Can be configured for operation as a standard “USB IO-Link Master
  • Firmware update supported

Advantages

  • Sensitive parts are located outside the EMC chamber
  • EMC robustness significantly better than required

Contact

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